Adder (electronics)
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In electronics, an adder is a device which will perform the addition, S, of two numbers. In computing, the adder is part of the ALU, and some ALUs contain multiple adders. Although adders can be constructed for many numerical representations, such as Binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement is being used to represent negative numbers it is trivial to modify an adder into an adder-subtracter.
For single bit adders, there are two general types. A half adder has two inputs, generally labelled A and B, and two outputs, the sum S and carry output Co. S is the two-bit xor of A and B, and Co is the two-bit and of A and B. Essentially the output of a half adder is the two-bit arithmetic sum of two one-bit numbers, with Co being the most significant of these two outputs.
The other type of single bit adder is the full adder which is like a half adder, but takes an additional input carry Ci. A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and or the two carry outputs. Equivalently, S could be made the three-bit xor of A, B, and Ci and Co could be made the three-bit majority function of A, B, and Ci. The output of the full adder is the two-bit arithmetic sum of three one-bit numbers.
The purpose of the carry input on the full-adder is to allow multiple full-adders to be chained together with the carry output of one adder connected to the carry input of the next most significant adder. The carry is said to ripple down the carry lines of this sort of adder, giving it the name ripple carry adder.
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[edit] Half adder
A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits.
- <math>S = A \oplus B</math>
- <math>C = A \cdot B</math>
Following is the logic table for a half adder:
| Input | Output | ||
|---|---|---|---|
| A | B | C | S |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
[edit] Full adder
A full adder is a logical circuit that performs an addition operation on three binary digits. The full adder produces a sum and carry value, which are both binary digits. It can be combined with other full adders (see below) or work on its own.
- <math>S = (A \oplus B) \oplus C_i</math>
- <math>C_o = (A \cdot B) + (C_i \cdot (A \oplus B)) = (A \cdot B) + (B \cdot C_i) + (C_i \cdot A)</math>
| Input | Output | |||
|---|---|---|---|---|
| <math>A</math> | <math>B</math> | <math>C_i</math> | <math>C_o</math> | <math>S</math> |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |
Note that the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because the only discrepancy between OR and XOR gates occurs when both inputs are 1; for the adder shown here, one can check this is never possible. Using only two types of gates is convenient if one desires to implement the adder directly using common IC chips.
[edit] Multiple-bit adders
It is possible to create a logical circuit using several full adders to add multiple-bit numbers. Each full adder inputs a <math>C_{in}</math>, which is the <math>C_{out}</math> of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.
The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Following the path from <math>C_{in}</math> to <math>C_{out}</math> shows 2 gates that must be passed through. Ergo, a 32-bit adder requires 31 carry computations and the final sum calculation for a total of <math>31*2 + 1 = 63</math> gate delays.
[edit] Carry look-ahead adders
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry lookahead adders. They work by creating Propagate and Generate signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry lookahead architectures are the Manchester carry chain and the Brent-Kung adder.
Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block.
Other adder designs include the conditional sum adder, carry skip adder, and carry complete adder.
[edit] Lookahead Carry Unit
By combining multiple carry look-head adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses 16 4-bit CLAs with two levels of LCUs.
[edit] 3:2 compressors
We can view a full adder as a 3:2 compressor: it sums three 1-bit inputs, and returns the result as a single 2-bit number. Thus, for example, an input of 101 results in an output of 1+0+1=10 (2). The carry-out represents bit 1 of the result, while the sum represents bit 0. Likewise, a half adder can be used as a 2:2 compressor.
3:2 compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the Carry save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.
[edit] See also
[edit] External links
- Hardware algorithms for arithmetic modules, includes description of several adder layouts with figures.da:Additionskredsløb (digital elektronik)
de:Volladdierer es:Sumador fi:Summain fr:Additionneur it:Full-adder ja:加算器 pl:Sumator (układ logiczny) sv:Adderare uk:Суматор
