Multiple patterning

From Wikipedia, the free encyclopedia

Multiple patterning is an extension of double patterning, a class of technologies developed for photolithography to enhance the feature density. Double patterning may be used as early as 65 nm node and will be the predominant lithography technique for 32 nm node. It can in principle be extended to 22 nm node as well. Beyond 22 nm node will require more than double patterning; perhaps multiple patterning would become appropriate.

There are several types of double patterning. The four most common types are: double exposure, spacer mask, heterogeneous mask, and intermediate pattern accumulation. It is expected that with appropriate iterations of double patterning techniques multiple patterning may be achieved.

1 Double Exposure
2 Spacer mask
3 Heterogeneous mask
4 Intermediate pattern accumulation
5 Concerns
6 References

[edit] Double Exposure

Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks. This technique is commonly used for patterns in the same layer which look very different or have incompatible densities or pitches. Unfortunately, the sum of the exposures cannot improve the minimum resolution limit. This technique allows manufacturability of minimum pitch features in a layout that may contain a variety of features. The 65 nm node saw the introduction of alternating phase-shift masks (see photomask) in manufacturing. This technology is typically a double exposure approach.

[edit] Spacer mask

A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes [1]. This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.

The main concerns with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. For the spacers to stay in place the adhesion to the underlying layer must exceed the adhesion to the adjacent material. This becomes more difficult if the spacer height exceeds the width (as commonly is the case). The spacer profile is typically sharp at the top due to the etch to remove the spacer material on horizontal surfaces. Hence the width actually decreases from the bottom to the top, which may complicate pattern transfer if the etch selectivity is not large. Pattern transfer is also complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other [1].

[edit] Heterogeneous mask

A heterogeneous mask approach is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample. This second layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is therefore a set of photoresist features in between hardmask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration[1].

[edit] Intermediate pattern accumulation

A "brute force" approach, intermediate pattern accumulation involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [2].

[edit] Concerns

With double or multiple patterning, the two main immediate concerns are reduced throughput and greater sensitivity to overlay error. The two concerns are an apparent tradeoff. For example, multi-pass scanning (a fraction of the exposure dose per scan) is an established technique to reduce feature placement error, but requires somewhat longer time for stage motion to carry out complete exposure. Generally, lithography tool manufacturers (notably ASML, Canon and Nikon) have always maintained a trend of improvement in both throughput and overlay, but multiple patterning makes this a necessity.

It is sometimes believed that throughput is reduced significantly by multiple patterning, but this is actually incorrect. Since a layer is split into multiple layers, the wafer effectively sees extra layers of processing added to a sequence already containing many layers. Since multiple patterning is only applied to at most a few critical layers, the overall throughput of a wafer is affected by a small amount.

Overlay error is a more significant concern, since it can arise from different sources. Aside from tool-based errors, overlay error can also result from exposing photomasks with different feature placement errors. The relative placement error of photomask features is avoided by using maskless lithography, since the reference mask (which is programmable) is fixed from exposure to exposure. Maskless lithography also allows higher de-magnification, which helps to minimize the feature placement error.

A third concern is increased cost due to higher consumption of materials and tool time, as well as new hardware and processes associated with multiple patterning. However, history has shown that the number of masks or layers used to manufacture chips has never decreased but only increased from one technology node to the next. The introduction of double patterning therefore will not be a significant departure from this trend of increasing cost, especially if introduced one critical layer at a time.