Flip-flop (electronics)
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- This article is about the electronic component. For other meanings, see flip-flop (disambiguation).
In digital circuits, the flip-flop, latch, or bistable multivibrator is an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. A flip-flop is controlled by one or two control signals and/or a gate or clock signal. The output often includes the complement as well as the normal output. As flip-flops are implemented electronically, they naturally also require power and ground connections.
Flip-flops can be either simple or clocked. Simple flip-flops consists of two cross coupled inverting elements – transistors, or NAND, or NOR-gates – perhaps augmented by some enable/disable (gating) mechanism. Clocked devices are specially designed for synchronous (time-discrete) systems and therefore ignores its inputs except at the transition of a dedicated clock signal (known as clocking, pulsing, or strobing). This causes the flip-flop to either change or retain its output signal based upon the values of the input signals at the transition. Some flip-flops change output on the rising edge of the clock, other on the falling edge.
Clocked flip-flops are typically implemented as master-slave devices* where two basic flip-flops (plus some additional logic) collaborates to make it insensitive to spikes and noise between the short clock transitions; they nevertheless also often include asynchronous clear or set inputs which may be used to change the current output independent of the clock.
Flip-flops can be further divided into types that have found common applicability in both asynchronous and clocked sequential systems: the SR ("set-reset"), D ("data"), T ("toggle"), and JK types are the common ones; all of which may be synthetisized from (most) other types by a few logic gates. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, <math>Q_{next}</math>, in terms of the input signal(s) and/or the current output, <math>Q</math>.
The first electronic flip-flop was invented in 1919 by William Eccles and F. W. Jordan (Radio Review Dez 1919 pages 143 following). It was initially called the Eccles-Jordan trigger circuit and consisted of two active elements (radio-tubes). The name flip-flop was later derived from the sound produced on a speaker connected with one of the backcoupled amplifiers output during the trigger process within the circuit.
* Early master-slave devices actually remained (half) open between the first and second edge of a clocking pulse; today most flip-flops are designed so they may be clocked by a single edge as this gives large benefits regarding noise immunity, without any significant downsides.
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[edit] Set-Reset flip-flops (SR flip-flops)
- See SR latch.
[edit] Toggle flip-flops (T flip-flops)
Image:T-Type Flip-flop.svg If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:
- <math>Q_{next} = T \oplus Q</math> (or, without benefit of the XOR operator, the equivalent: <math>Q_{next} = T\overline{Q} + \overline{T}Q</math> )
and can be described in a truth table:
| <math>T</math> | <math>Q</math> | <math>Q_{next}</math> | Comment |
|---|---|---|---|
| 0 | 0 | 0 | hold state |
| 0 | 1 | 1 | hold state |
| 1 | 0 | 1 | toggle |
| 1 | 1 | 0 | toggle |
A toggle flip-flop composed of a single RS flip-flop becomes an oscillator, when it is clocked. To achieve toggling, the clock pulse must have exactly the length of half a cycle. While such a pulse generator can be built, a toggle flip-flop composed of two RS flip-flops is the easy solution.
[edit] JK flip-flop
Image:JK FF impulse diagram.png The JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R = 1 condition as a "flip" command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 results in a D-type flip-flop. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop or a T flip-flop.
The characteristic equation of the JK flip-flop is:
<math>Q_{next} = J\overline Q + \overline KQ</math>
and the corresponding truth table is:
| J | K | Qnext | Comment |
| 0 | 0 | <math>Q_{prev} \ </math> | hold state |
| 0 | 1 | <math>0 \ </math> | reset |
| 1 | 0 | <math>1 \ </math> | set |
| 1 | 1 | <math>\overline{Q_{prev}} </math> | toggle |
The origin of the name for the JK flip-flop is detailed by P. L. Lindley, a JPL engineer, in a letter to EDN, an electronics newsletter. The letter is dated June 13, 1968, and was published in the August edition of the newsletter. In the letter, Mr. Lindley explains that he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is responsible for coining the term while working at Hughes Aircraft.
Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Given the size of the system that he was working on, Dr. Nelson realized that he was going to run out of letters, so he decided to use J and K as the set and reset input of each flip-flop in his system (using subscripts or somesuch to distinguish the flip-flops), since J and K were "nice, innocuous letters."
Dr. Montgomery Phister, Jr., an engineer under Dr. Nelson at Hughes, picked up the idea that J and K were the set and reset input for a "Hughes type" of flip-flop, which he then termed "J-K flip-flops," a name that he carried with him when he left for Scientific Data Systems in Santa Monica.
[edit] D flip-flop
The D flip-flop can interpreted as a primitive delay line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input. It is called delay flip flop since the output takes the value in the Data-in.
The characteristic equation of the D flip-flop is:
- <math>Q_{next} = D \,</math>
and the corresponding truth table is:
D Q > Qnext 0 X Rising 0 1 X Rising 1
The flip flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices.
The advantage of this circuit over the D-type latch is that it "captures" the signal at the moment the clock goes high, and subsequent changes of the data line do not matter, even if the signal line has not yet gone low again.
[edit] Master-slave D flip-flop
A master-slave D flip-flop is created by connecting two gated D latches in series, and invert the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.
Image:Negative-edge triggered master slave D flip flop.png
For a positive-edge triggered master-slave D flip-flop, the first D latch is transparent during a high enable, and the second D latch is transparent during a low enable. Thus the full D flip-flop is never fully transparent. When the enable goes from low to high (0 to 1), the D input goes through the first (master) latch to the second (slave) latch. When the enable drops back to low (1 to 0), the output of the master latch is "locked", and the slave latch is transparent. When the enable goes back high (0 to 1), the slave latch will lock, and thus preserve the output until the next strobing of the enable (or clock).
By removing the left-most inverter in the above circuit, a D-type flip flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this:
D Q > Qnext 0 X Falling 0 1 X Falling 1
Most D-type flip-flops in ICs have the capability to be set and reset, much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops.
Inputs Outputs S R D > Q Q' 0 1 X X 0 1 1 0 X X 1 0 1 1 X X 1 1
By settting S = R = 0, the flip-flop can be used as described above.
[edit] Edge-triggered D flip-flop
A more efficient way to make a D flip-flop is not as easy to understand, but it works the same way. While the master-slave D flip flop is also triggered on the edge of a clock, its components are each triggered by clock levels. The "edge-triggered D flip flop" does not have the master slave properties.
[edit] Uses
- A single flip-flop can be used to store one bit, or binary digit, of data.
- Static RAM, which is the primary type of memory used in registers to store numbers in computers and in many caches, is built out of flip-flops.
- Any one of the flip-flop types can be used to build any of the others. The data contained in several such flip-flops may represent the state of a sequencer, the value of a counter, an ASCII character in a computer's memory or any other piece of information.
- One use is to build finite state machines from electronic logic. The flip-flops remember the machine's previous state, and digital logic uses that state to calculate the next state.
- The T flip-flop is useful for constructing various types of counters. Repeated signals to the clock input will cause the flip-flop to change state once per high-to-low transition of the clock input, if its T input is "1". The output from one flip-flop can be fed to the clock input of a second and so on. The final output of the circuit, considered as the array of outputs of all the individual flip-flops, is a count, in binary, of the number of cycles of the first clock input, up to a maximum of 2n-1, where n is the number of flip-flops used. See: Counters
- One of the problems with such a counter (called a ripple counter) is that the output is briefly invalid as the changes ripple through the logic. There are two solutions to this problem. The first is to sample the output only when it is known to be valid. The second, more widely used, is to use a different type of circuit called a synchronous counter. This uses more complex logic to ensure that the outputs of the counter all change at the same, predictable time. See: Counters
- Frequency division: a chain of T flip-flops as described above will also function to divide an input in frequency by 2n, where n is the number of flip-flops used between the input and the output.
[edit] Timing and metastability
A flip-flop in combination with a Schmitt trigger can be used for the implementation of an arbiter in asynchronous circuits.
Clocked flip-flops are prone to a problem called metastability, which happens when a data or control input is changing at the instant of the clock pulse. The result is that the output may behave unpredictably, taking many times longer than normal to settle to its correct state, or even oscillating several times before settling. Theoretically it can take infinite time to settle down. In a computer system this can cause corruption of data or a program crash.
In many cases, metastability in flip-flops can be avoided by ensuring that the data and control inputs are held constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased.
So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).
When connecting flip-flops in a chain, it is important to ensure that the tCO of the first flip-flop is longer than the hold time (tH) of the second flip-flop, otherwise the second flip-flop will not receive the data reliably. The relationship between tCO and tH is normally guaranteed if both flip-flops are of the same type.
[edit] Flip-Flop integrated circuits
Integrated circuit (ICs) can be found with one or more Flip-flop circuits on board. For example, the 7473 Dual JK Master-Slave Flip-flop or the 74374, an octal D Flip-flop, in the 7400 series.
[edit] See also
[edit] External links
| Wikimedia Commons has media related to: |
- Summary of flip-flop types
- Another summary of flip-flop types
- Explanation of How Flip Flops Work with Logic Gate Diagrams
- Flip-flops interactive (requires Java)ar:قلاب
bs:Flip-flop cs:Klopný obvod da:Flip-flop (digital elektronik) de:Flipflop es:Biestable fi:Kiikku (tietokonetekniikka) fr:Bascule hr:Bistabil it:Flip-flop he:פליפ פלופ lv:Trigeris nl:Flip-flop ja:フリップフロップ pl:Przerzutnik pt:Flip-flop sl:Bistabilni multivibrator sv:Vippa zh:触发器
